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INTEGRATED CIRCUITS
DATA SHEET
TDA8310A PAL/NTSC colour processor for PIP applications
Product specification Supersedes data of 1995 Nov 29 File under Integrated Circuits, IC02 1996 Jan 25
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
FEATURES * Video switch with 2 CVBS inputs. One input can be switched between CVBS and Y/C and the circuit can automatically detect whether the incoming signal is CVBS or Y/C * Integrated chrominance trap and bandpass filters (automatically calibrated) * Integrated luminance delay line * Automatic PAL/NTSC decoder which can decode all standards available in the world * Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications * Horizontal PLL with an alignment-free horizontal oscillator * Vertical count-down circuit * RGB/YUV and fast blanking switch with 3-state output and active clamping * Low dissipation (560 mW) * Small amount of peripheral components compared with competition ICs. GENERAL DESCRIPTION
TDA8310A
The TDA8310A is an alignment-free PAL/NTSC colour processor for Picture-in-Picture (PIP) applications. The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted in the TDA8310A. Therefore, the circuit contains an input signal selector, a PAL/NTSC colour decoder, horizontal and vertical synchronization and an RGB/YUV switch. The input signal selector has 2 CVBS inputs. One of the inputs can be switched between CVBS and Y/C and the circuit can automatically detect whether the incoming signal is CVBS or Y/C. The output signals for the PIP processor are; Luminance signal Colour difference signals (U and V) Horizontal and vertical synchronization pulses. The RGB/YUV switch can select between two RGB or YUV sources, e.g. between the PIP processor and the SCART input signal. The supply voltage for the IC is 8 V. It is available in a 52-pin SDIP package.
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8310A SDIP52 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) VERSION SOT247-1
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
QUICK REFERENCE DATA SYMBOL VP IP V17,20(p-p) V16(p-p) Vi(p-p) supply current PARAMETER supply voltage (pins 19 and 41) - - - - MIN. 7.2 TYP. 8.0 70
TDA8310A
MAX. 8.8 1.4 - - 1.3 V
UNIT mA
Input voltages CVBS/Y input voltage (peak-to-peak value) chrominance input voltage (peak-to-peak value) RGB/YUV input signal voltage amplitude (peak-to-peak value) 1.0 0.3 - V V V
Output signals Vo(p-p) V50(p-p) V51(p-p) V39 V36 Gv Vcontrol luminance output voltage (peak-to-peak value) (B-Y) output voltage (peak-to-peak value) (R-Y) output voltage (peak-to-peak value) horizontal sync pulse output voltage vertical sync pulse output voltage voltage gain of the RGB switches - 1.06 0.84 - - -0.5 1.4 1.33 1.05 4.0 4.0 0 - - 1.6 1.26 - - +0.5 V V V V V dB
Control voltage control voltage for HUE 0 5.0 V
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INTB VP1 PH1LF 37 DECBG 35 DECDIG 21 19 41 30 39 36 40 VP2 HOUT VOUT SAND COINCIDENCE/ NOISE DETECTOR PHASE DETECTOR VCO + CONTROL 10 PULSE SHAPER SANDCASTLE GENERATOR R1 11 12 13 i.c. n.c. 22, 29 33, 34 SYNC SEPARATOR VERTICAL SYNC SEPARATOR HORIZONTAL/ VERTICAL DIVIDER RGB/YUV SWITCH 14 CLAMP 8 7 6 DECFT 5 15 R G B BLANK R2 G2 B2 BLANK2 IDENT HUE BLANK1 G1 B1
BLOCK DIAGRAM
Philips Semiconductors
PAL/NTSC colour processor for PIP applications
TDA8310A
1 2 3
handbook, full pagewidth
4
CHROMINANCE BANDPASS CHROMINANCE TRAP FILTER TUNING CVBSSW 32 REF AUTOMATIC Y/C DETECTOR INPUT SELECTOR PAL/NTSC DECODER LUMINANCE DELAY LINE 31 20 17 9 16 47 48 46 PLL CVBSEXT GND2 CVBSINT CHROMAI SECAM 45 XTAL4 44 XTAL3 43 XTAL2 42 XTAL1 R/W COLOUR2 LOGIC2 BY RY GND1 GND3 27 26 25 24 23 50 51 18 38 SYSTSW CHROMAO COLOUR1 LOGIC1
52
4 28 49
Y
MGD128
Product specification
TDA8310A
Fig.1 Block diagram.
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
PINNING SYMBOL R2 G2 B2 IDENT BLANK B G R SYSTSW R1 G1 B1 BLANK1 CLAMP DECFT CHROMAI CVBSEXT GND1 VP1 CVBSINT DECDIG i.c. LOGIC2 LOGIC1 COLOUR2 COLOUR1 R/W PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 DESCRIPTION RED input 2 (PIP) GREEN input 2 (PIP) BLUE input 2 (PIP) colour standard identification output blanking output BLUE output GREEN output RED output CVBS/system switch RED input 1 GREEN input 1 BLUE input 1 blanking input 1 clamping pulse input decoupling filter tuning chrominance input external CVBS/Y input ground 1 (0 V) supply voltage 1 (+8 V) internal CVBS input decoupling digital supply rail internally connected (test purposes) crystal logic 2 input/output crystal logic 1 input/output colour system logic 2 input/output colour system logic 1 input/output read/write selection input n.c. n.c. DECBG VOUT PH1LF GND3 HOUT SAND VP2 XTAL1 XTAL2 XTAL3 XTAL4 PLL CHROMAO SECAM Y B-Y R-Y BLANK2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 SYMBOL HUE i.c. INTB GND2 CVBSSW PIN 28 29 30 31 32
TDA8310A
DESCRIPTION HUE control input internally connected (test purposes) internal bias ground 2 (0 V) CVBS positive/negative modulation control switch input not connected not connected bandgap decoupling vertical sync output pulse phase 1 loop filter ground 3 (0 V) horizontal sync output pulse sandcastle pulse output supply voltage 2 (+8 V) 4.4336 MHz crystal 3.5820 MHz crystal for PAL-N 3.5756 MHz crystal for PAL-M 3.5795 MHz crystal for NTSC PLL colour filter chrominance output for TDA8395 SECAM reference output Y output B-Y output R-Y output blanking/insertion input 2 (PIP)
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
TDA8310A
handbook, halfpage
R2 G2 B2 IDENT BLANK B G R SYSTSW
1 2 3 4 5 6 7 8 9
52 BLANK2 51 R-Y 50 B-Y 49 Y 48 SECAM 47 CHROMAO 46 PLL 45 XTAL4 44 XTAL3 43 XTAL2 42 XTAL1 41 VP2 40 SAND
R1 10 G1 11 B1 12 BLANK1 13
TDA8310A
CLAMP 14 DECFT 15 CHROMAI 16 CVBSEXT 17 GND1 18 VP1 19 CVBSINT 20 DECDIG 21 i.c. 22 LOGIC2 23 LOGIC1 24 COLOUR2 25 COLOUR1 26
MGD127
39 HOUT 38 GND3 37 PH1LF 36 VOUT 35 DECBG 34 n.c. 33 n.c. 32 CVBSSW 31 GND2 30 INTB 29 i.c. 28 HUE 27 R/W
Fig.2 Pin configuration.
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
FUNCTIONAL DESCRIPTION CVBS switch The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y/C. The circuit contains an identification circuit which can automatically switch between the CVBS and Y/C signals. It is also possible to force the switch to CVBS or Y/C. Synchronization circuit The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used to detect whether the line oscillator is synchronized and for transmitter identification. The first PLL has a very high static steepness this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency. The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value. The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the output pulse is 5.4 s, the front edge of this pulse coincides with the front edge of the sync pulse at the input. The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 s. Both the horizontal and vertical output pulses will always be available at the outputs even when no input signal is available. In addition to the horizontal and vertical sync pulse outputs the IC has a sandcastle pulse output which contains burst key and blanking pulses. Integrated video filters
TDA8310A
The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. When a Y/C signal is supplied to the input the chrominance trap is automatically switched off by the Y/C detection circuit however, it is also possible to force the filters in the CVBS or Y/C position. The luminance delay line is also realised by gyrator circuits. Colour decoder The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. The 90 phase shift for the reference signal is achieved internally. The colour decoder is very flexible. Together with the SECAM decoder (TDA8395) an automatic multistandard decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the IC. The decoder can be forced to one of the standards via the `forced mode' pins. The crystal pins which are not used must be connected to the positive supply line via a 8.2 k resistor. It is also possible to connect the non-used pins with one resistor to the positive supply line. In this event the resistor must have a value of 8.2 k divided by the number of pins. The chrominance output signal of the video switch is externally available and must be used as an input signal for the SECAM decoder. RGB/YUV switch The RGB/YUV switch is for switching between two RGB or YUV video sources. The outputs of the switch can be set to high-impedance state so that other switches can be used in parallel. The switch is controlled via pins 13 and 52. The details of switch control are shown in Table 4.
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VP Tstg Tamb Tsld Tj supply voltage storage temperature operating ambient temperature soldering temperature for 5 s maximum operating junction temperature PARAMETER - -25 -25 - - MIN.
TDA8310A
MAX. 9.0 +150 +70 260 150 V
UNIT C C C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 40 UNIT K/W
CHARACTERISTICS VP = 8 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VP IP1 IP2 Ptot Rbias supply voltage (pins 19 and 41) supply current (pin 19) supply current (pin 41) total power dissipation value of resistor to be connected between pin 30 and the positive supply line 7.2 45 3 - - 8.0 65 5 560 10 8.8 80 10 - - V mA mA mW k PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CVBS and Y/C switch INTERNAL CVBS AND EXTERNAL CVBS/Y INPUTS (PINS 20 AND 17) V20,17(p-p) I20,17 Vclamp Iclamp V16(p-p) V16(p-p) RI CI CVBS/Y input voltage (peak-to-peak value) input current top sync clamping voltage level clamping input current notes 1 and 3 - - - 80 - 1.0 14 note 1 - 1 4 3.3 100 1.4 6 - - - - 26 5 V A V A V V k pF
CHROMINANCE INPUT (PIN 16) chrominance input voltage (peak-to-peak value) notes 1, 4 and 11 0.3 - 20 -
input signal amplitude before clipping note 2 occurs (peak-to-peak value) chrominance input resistance chrominance input capacitance
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8310A
MAX.
UNIT
CHROMINANCE OUTPUT (PIN 47) V47(p-p) ZO VO V32 V32 ZI ISS output signal voltage amplitude (peak-to-peak value) output impedance DC output voltage open-circuit output 0.18 200 1.2 - 3.9 25 note 2 50 0.20 250 1.4 - - - - 0.22 300 1.6 V V
SWITCH CONTROL INPUT FOR INTERNAL/EXTERNAL POSITIVE/NEGATIVE MODULATION (PIN 32); note 5 internal CVBS signal selected external CVBS or Y/C signal selected input impedance suppression of non-selected video input signal 1.0 VP - - V V k dB
SWITCH CONTROL INPUT FOR EXTERNAL CVBS OR Y/C SELECTION (PIN 9) V9 V9 V9 ZI filters switched to CVBS condition filters switched to Y/C condition automatic selection of CVBS or Y/C input impedance note 6 - 2.0 3.9 25 - - - - 1.0 3.0 VP - V V V k
Chrominance filters, luminance delay line and luminance output CHROMINANCE TRAP CIRCUIT ftrap QF SR trap frequency trap quality factor colour subcarrier rejection notes 2 and 7 - - 20 - note 2 - 0 fosc 2 - fosc 3 - - - - - 100 ns dB MHz
CHROMINANCE BANDPASS CIRCUIT fc QBP Y DELAY LINE td difference in delay time between the luminance and the demodulated chrominance signals bandwidth of internal delay line note 2 50 centre frequency bandpass quality factor MHz
B
note 2
8
- 1.0 100 2.9 0.5 -
- 1.2 120 3.1 - 2
MHz
Y OUTPUT (PIN 49) V49(b-w) ZO V49(DC) Ibias Isource output signal voltage amplitude (black-to-white value) output impedance DC output voltage level (top sync) internal bias current of NPN emitter follower output transistor maximum source current note 23 0.8 80 2.7 0.4 - V V mA mA
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8310A
MAX.
UNIT
Horizontal and vertical synchronization circuits SYNC VIDEO INPUT (PINS 17 AND 20) V17,20 SL sync pulse voltage amplitude slicing level note 1 note 8 50 - 22 300 50 - - - - mV % s
VERTICAL SYNC
tW
width of the vertical sync pulse without sync instability
note 9
HORIZONTAL OSCILLATOR ffr ffr fosc/VP fosc fosc(max) free running frequency spread on free running frequency frequency variation with respect to the supply voltage frequency variation with temperature maximum frequency deviation at the start of the horizontal output VP = 8 V 10%; note 2 - - - 15625 - 0.2 - - - 2 0.5 80 75 Hz % % Hz %
Tamb = 0 to 70 C; note 2 - no calibration -
HORIZONTAL PLL (FILTER CONNECTED TO PIN 37); note 18 fHR fCR S/N holding range PLL catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point note 2 - 0.6 14 0.9 0.9 20 1.2 - 26 kHz kHz dB
HYS
1
3
6 - 0.6 2 2 - -
dB
HORIZONTAL OUTPUT (PIN 39) VOH VOL Isink Isource tW td HIGH level output voltage LOW level output voltage sink current source current pulse width delay between the positive edge of the horizontal output pulse and the start of the horizontal sync pulse at the input IO = 2 mA IO = 2 mA 2.4 - - - - - 4.0 0.3 - - 5.4 0 V V mA mA s s
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL PARAMETER CONDITIONS - 45 - 488 IOL = 2 mA IOL = 2 mA 2.4 - - - - - MIN. TYP.
TDA8310A
MAX. - 64.5 722 - 0.6 2 2 - -
UNIT
VERTICAL OUTPUT (PIN 36); note 10 ffr flock free running frequency locking range divider value not locked locking range VOH VOL Isink Isource tW td HIGH level output voltage LOW level output voltage sink current source current pulse width delay between the start of the vertical sync pulse at the input and the positive edge of the output pulse 50/60 - - 4.0 0.3 - - 380 37.5 Hz Hz lines lines/ frame V V mA mA s s
625/525 -
SANDCASTLE PULSE OUTPUT (PIN 40); note 16 VO VO ZO tW output voltage during scan output voltage during burst key output impedance during blanking pulse width burst key line blanking vertical blanking td delay of start of burst key to start of sync 3.3 8.4 - 5.2 3.5 8.7 14 5.4 3.7 9.0 - 5.6 s s lines s IO = 1 mA; note 24 IO = 1 mA; note 24 - 4.1 1.0 - - - 0.9 5.2 - V V M
Colour demodulation part CHROMINANCE AMPLIFIER ACCcr V THRon HYSoff ACC control range change in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF strong input signal noisy input signal ACL CIRCUIT chrominance burst ratio at which the ACL starts to operate 2.3 - 2.7 note 2 S/N 40 dB 0 0 +3 +1 +6 +8 dB dB note 11 26 - -38 - - -41 - 2 -44 dB dB dB
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL REFERENCE PART PARAMETER CONDITIONS MIN. TYP.
TDA8310A
MAX.
UNIT
Phase-locked loop; note 12
fCR catching range phase shift for a 300 Hz deviation of note 2 the oscillator frequency 300 - 500 - - 2 Hz deg
Oscillator
TCosc fosc RI RI CI R temperature coefficient of fosc fosc deviation with respect to VP input resistance (pins 43 to 45) input resistance (pin 42) input capacitance (pins 42 to 45) note 2 VP = 8 V 10%; note 2 fi = 3.58 MHz; note 1 fi = 4.43 MHz; note 1 note 1 - - - - - 7.8 2.0 - 1.5 1 - 8.2 2.5 250 - - 10 8.6 Hz/K Hz k k pF k
required resistance to VP for a crystal note 20 pin which is not used
HUE CONTROL INPUT (PIN 28); note 21 HUEcr Vcontrol RI V50(p-p) V51(p-p) HUE control range control voltage to switch the colour PLL in the free-running mode input resistance -(B-Y) output signal voltage amplitude (peak-to-peak value) -(R-Y) output signal voltage amplitude (peak-to-peak value) spread of signal amplitude ratio PAL/NTSC ZO B V50(p-p) V51(p-p) V51(p-p) VO/T VO/VP Ibias Isource output impedance (R-Y)/(B-Y) output bandwidth of demodulators (B-Y) residual carrier output voltage (peak-to-peak value) (R-Y) residual carrier output voltage (peak-to-peak value) H/2 ripple at (R-Y) output (peak-to-peak value) change of output signal amplitude with temperature change of output signal amplitude with supply voltage internal bias current of NPN emitter follower output transistor maximum source current -3 dB; note 19 f = fosc f = 2fosc f = fosc f = 2fosc only burst fed to input note 2 note 2 see also Fig.3 note 12 35 VP - 1 45 40 - - 1.33 1.05 - - 650 - - - - - 0.1 - 0.20 - - - - 1.60 1.26 +1 500 - 1 5 1 5 25 - 0.1 - 1 deg V k
DEMODULATOR OUTPUTS (PINS 50 AND 51) note 25 note 25 note 2 1.06 0.84 -1 - - - - - - - - - 0.16 - V V dB kHz mV mV mV mV mV %/K dB mA mA
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8310A
MAX.
UNIT
DEMODULATION ANGLE AND GAIN RATIO demodulation angle G gain ratio of both demodulators G(B-Y) to G(R-Y) 85 1.60 90 1.78 95 1.96 deg
REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 48) fref V48(p-p) VO VO I48 reference frequency output signal amplitude (peak-to-peak value) output voltage level output voltage level required current to force the decoder in SECAM mode PAL/NTSC identified no PAL/NTSC; SECAM (by TDA8395) identified note 13 - 0.2 1.5 4.3 120 4.43 0.25 1.6 4.5 - - 0.3 1.7 4.7 - MHz V V V A
STANDARD IDENTIFICATION AND FORCED SYSTEM SWITCHING (PINS 4 AND 23 TO 27); note 14 VI/O input/output voltage in `low' condition in `high' condition VI(max) Iload II maximum input voltage maximum load current (pins 23 to 26) input current (pins 23 to 26) in `low' or `high' condition when connected to VP RI VO input resistance (pin 27) output voltage (pin 4) during PAL during SECAM ZO Iload RGB switch RGB INPUTS (PINS 1 TO 3 AND 10 TO 12) Vi(p-p) ZI Vclamp ILI Iclamp signal voltage amplitude (peak-to-peak value) input impedance active clamping voltage level input leakage current active clamping current note 2 - 100 2.6 - -200 - - 2.8 - - 1.3 - 3.0 3 +200 V k V A A output impedance (pin 4) during NTSC maximum load current (pin 4) note 17 IO = 0.5 mA; notes 17 and 24 note 22 - - 80 - 4.1 1 - - - - - - - - 1 10 - 0.9 5.5 - 0.5 A A k V V M mA note 22 - 4.0 - - - - - - 1.0 5.3 VP 1 V V V mA
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL PARAMETER CONDITIONS - 0.9 0 - - 4 MIN. TYP. -0.2 - - - - -
TDA8310A
MAX. -0.3 3.0 0.5 50 70 VP
UNIT
FAST BLANKING/SWITCH INPUTS (PINS 13 AND 52); note 15 II VIH VIL td td V13 input current HIGH level input voltage LOW level input voltage delay between input and output pulse delay between switch input and RGB output input voltage on pin 13 to make RGB outputs and the fast blanking output high-ohmic mA V V ns ns V
CLAMPING PULSE INPUT (PIN 14) VIH VIL ZI Gv Gdiff ZO ZO(off) VO Vos Isource(max) Ibias ISS HIGH level input voltage LOW level input voltage input impedance 4.0 - 1 -0.5 - - f = 10 MHz open-circuit output 100 1.2 - - 0.16 f = 5 MHz; note 2 f = 10 MHz; note 2 f = 22 MHz; note 2 ct crosstalk between the two RGB channels f = 5 MHz; note 2 f = 10 MHz; note 2 f = 22 MHz; note 2 B bandwidth of the RGB channels gain reduction -0.5 dB gain reduction -1 dB gain reduction -3 dB td delay from RGB input to output note 2 CL = 20 pF; note 2 5 10 22 - - - - - - - - 20 MHz MHz MHz ns 60 50 40 -60 -50 -40 4.5 - - 0 - - - 1.4 - - 0.2 - - - - - - VP 1 - +0.5 0.5 150 - 1.6 5 1 - - - - - - - V V M
RGB OUTPUTS (PINS 6 TO 8) voltage gain of the switches gain difference of the three channels output impedance output impedance in the `off' state output voltage during blanking blanking off-set voltage of the two sources maximum source current internal bias current of NPN emitter follower output transistor input signal suppression when RGB outputs are high-ohmic f = 1 MHz dB dB k V mV mA mA dB dB dB dB dB dB
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - TYP.
TDA8310A
MAX.
UNIT
FAST BLANKING OUTPUT (PIN 5) VOH VOL ZO ZO(off) tr tf td Iload Notes 1. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 3. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 4. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p). 5. The IC has two 3-level switch control inputs for the selection of the video signal for the decoder and synchronization circuits. The video source for internal or external signal is selected via pin 32, also the polarity of the demodulation for the internal signal. When the video switch is in the external position the voltage level of pin 9 determines whether the video filters are switched to CVBS or Y/C. It is also possible via pin 9 to select an automatic detection of the Y/C signal. 6. This value is internally generated when the pin is left open-circuit (the minimum value of the series resistor is 25 k). 7. The -3 dB bandwidth of the circuit can be calculated by means of the following equation: 1 f -3 dB = f osc 1 - ------- 2Q 8. The slicing level is independent of the sync pulse amplitude. 9. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 s. 10. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 2 search modes of operation: a) The `large window' mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) The `narrow window' mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. HIGH level output voltage LOW level output voltage output impedance output impedance in the `off' state rise time of the output pulse fall time of the output pulse delay difference between fast blanking and RGB at the outputs maximum load current 2 0 - 100 - - - - 3 0.3 300 - 30 30 30 1 V V k ns ns ns mA
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
TDA8310A
11. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) as given in Characteristics first parameter of Section "Chrominance input (pin 16)" the dynamic range of the ACC is +6 and -20 dB. 12. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than -3 dB with respect to the fundamental frequency for a damping resistance of 1 k, oscillation at the fundamental frequency is guaranteed. The spurious response of the 3.58 MHz crystal must be lower than -3 dB with respect to the fundamental frequency for a damping resistance of 1.5 k. The catching and detuning range are measured for nominal crystal parameters. These are: a) Load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz b) Motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal) c) Parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal). The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. The free-running frequency of the oscillator can be checked by the HUE control pin to the positive supply rail. In that condition the colour killer is not active so that the frequency offset is visible on the screen. When two or more crystals are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator continuously switching between the various frequencies. 13. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of 4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus avoiding crosstalk with the incoming SECAM signal during scan. 14. The identified colour standard can be read from the IC in two ways: a) From the voltage level of pin 4. The voltage during the demodulation of the various standards is given in the last three parameters of this section. b) From the pins 23 to 26 when pin 27 is in the `read' mode. When pin 27 is in the `write' mode the colour decoder can be forced to one of the colour standards. The levels for the various standards are given in Tables 1, 2 and 3. 15. The control possibilities of the RGB switch via pins 13 and 52 are shown in Table 4. 16. To obtain a simple interface between the TDA8310A and the PIP processor the sandcastle output has been designed such that the output is pulled down during scan and pulled up during the burst key pulse. During blanking the output is high-ohmic and therefore the output voltage is determined by the load. 17. The output of pin 4 is designed similar to the sandcastle output. The output is pulled down during PAL and pulled up during SECAM. During NTSC the pin is floating so that the output level is determined by the load. 18. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time constant is switched to `slow' when excessive noise is present in the signal. This occurs when the internal video signal is selected or for an external CVBS signal when the chrominance input (pin 16) is left open-circuit. The time constant is always `fast' when the chrominance input pin is connected to ground and the input is switched to the Y/C mode. In the `fast' mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. During weak signal conditions (noise detector active) the phase detector is gated and the width of the gate pulse has a value of 5.7 s so that the effect of the noise is reduced to a minimum. The output current of the phase detector for the various conditions is shown in Table 5. 19. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the demodulator low-pass filter is approximately 1 MHz.
1996 Jan 25
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Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
TDA8310A
20. The crystal pins which are not used must be connected to the positive supply line via an 8.2 k resistor. It is also possible to connect the non-used pins together and use a resistor with a value of 8.2 k divided by the number of pins which are not used. 21. When this pin is left open-circuit the HUE control is set to the nominal value. 22. When one or more pins have to be connected to the positive supply line the total current must be limited to 40 A. This can be achieved by connecting these pins together and connecting them to a positive supply line via a 100 k resistor. When separate resistors are used a resistor with a higher value must be used so that the total current is limited to the required level. 23. This output signal value is obtained when the CVBS or Y input signal at pins 17 and/or 20 has an amplitude of 0.7 V (black-to-white value). 24. The output buffer consists of a combination of a PMOS and an NMOS. The maximum output impedance in the low state can be calculated by dividing the maximum output voltage (for this parameter 0.9 V) by the specified current. For the high state this resistance can be calculated by dividing the difference between the maximum and minimum output voltage by the specified current. The output impedance is independent of the value of the output current. 25. These output signal values are obtained for a colour bar input signal with 75% saturation.
1996 Jan 25
17
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
Table 1 Read/write pin input (pin 27) MODE Decoder automatic Forced decoder mode LEVEL LOW HIGH
TDA8310A
Table 5 Output current of phase detector CURRENT PHASE SCAN DETECTOR (A) DURING Weak signal and synchronized Strong signal and synchronized Not synchronized 30 180 180 VERTICAL RETRACE (A) 30 270 270 GATED YES/NO YES (5.7 s) NO NO
Table 2 Colour system logic (pins 25 and 26) PIN 25 LOW LOW HIGH HIGH PIN 26 LOW HIGH LOW HIGH PAL NTSC SECAM STANDARD auto/no colour
MBE018
handbook, halfpage 40
Table 3 Crystal logic (pins 23 and 24) PIN 23 LOW LOW HIGH HIGH PIN 24 LOW HIGH LOW HIGH SELECTED CRYSTAL (MHz) 4.43 3.579 (NTSC) 3.575 (PAL-M) 3.582 (PAL-N)
(deg)
20
0
Table 4 Control logic RGB switch (pins 13 and 52) PIN 13 LOW LOW HIGH HIGH PIN 52 LOW HIGH LOW HIGH RGB OUTPUT black RGB 2 RGB 1 RGB 2 FAST BLANKING OUTPUT LOW HIGH HIGH HIGH
40 0 1 2 3 4 (V) 5 20
Fig.3 HUE control curve.
1996 Jan 25
18
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
PACKAGE OUTLINE SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
TDA8310A
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
1996 Jan 25
19
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8310A
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jan 25
20
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
NOTES
TDA8310A
1996 Jan 25
21
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
NOTES
TDA8310A
1996 Jan 25
22
Philips Semiconductors
Product specification
PAL/NTSC colour processor for PIP applications
NOTES
TDA8310A
1996 Jan 25
23
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/02/pp24 Document order number: Date of release: 1996 Jan 25 9397 750 00589

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